1. Field of the Invention
The present invention relates to a power-on signal generating circuit, and more particularly to a power-on signal generating circuit operating with a low-dissipation current.
2. Related Art
In a digital IC (Integrated Circuit), there may be a case that an internal portion of the IC must be initialized when it is powered. For this reason, a power-on signal generating circuit is built in the IC for generating a signal for the initialization when the IC is powered. A conventional power-on circuit is shown in FIG. 1.
In the circuit shown in FIG. 1, the power-on signal generating circuit includes: a power supply terminal 1; a P-channel type field effect transistor (FET) T11 a source of which is connected to the power supply terminal 1; a resistor R3 one terminal of which is connected to the power supply terminal 1; and a capacitor C4 one terminal of which is connected to the power supply terminal 1. A gate and a drain of the P-channel FET 11, one terminal of a resistor R2, one terminal of a capacitor C3, and a gate of an N-channel FET T12 are mutually connected to a node Nd. The other terminal of the resistor R3, a drain of the N-channel FET T12, the other terminal of a capacitor C4, an input of an inverter B3 are mutually connected to a node Ne. An output of the inverter B3 is connected to an output terminal. The other terminal of the resistor R2, the other terminal of the capacitor C3, and a source of the N-channel FET T12 are connected to a ground terminal 2.
FIG. 2 is a characteristic diagram showing a relation between an output voltage of the power-on signal generating circuit shown in FIG. 1 with respect to time.
More specifically, FIG. 2 shows a relation among a potential V1 of the power supply terminal 1, a potential of the node Nd, a potential of the node Ne, and a potential of the output terminal 3 when the circuit is powered. The potential V1 of the power supply terminal 1 raises in accordance with elapse of time and exceeds a threshold voltage Vtp of the P-channel FET T11 in the neighbor of the time t4. The potential of the node Nd raises in accordance with the elapse of time while retaining a value of (V1-Vtp) from approximately time t4. In the neighborhood of time t5, the potential of the node Nd exceeds a threshold voltage of the N-channel FET T12, and thus the N-channel FET T12 is conducted. As a result, a potential of the node Ne changes from the potential V1 of the power supply terminal 1 to the potential of the ground terminal 2. For this reason, the output of the inverter B3 is inverted at time t6 where the curve of the potential of the node Ne crosses with the logical threshold voltage of the inverter B3. More specifically, the potential of the output terminal 3 becomes the ground potential (0 V) during a period of t0 through t6, and becomes the potential V1 of the power supply terminal 1 after the time t6. Accordingly, when the circuit is powered, the potential of the output terminal 3 becomes at "Low" level during a period of time t0 through t6, and changes at "High" level after the time t6. The period in which the signal which is output from the output terminal 3 and at the "Low" level is used as the power-on signal.
The current dissipated in the power-on signal generating circuit is a sum of currents IR2 and IR3 flowing through the resistor R2 and R3.
The current IR2 is expressed as the equation (1): EQU IR2=Vd/r2 (1)
wherein Vd is a potential of the node Nd and r2 is a resistance value of the resistor R2.
If an ON-resistance of the FET T11 is small enough with respect to the resistor R2, the above equation (1) can be expressed as the equation (1'). EQU IR2=(V1-.vertline.Vtp.vertline.)/r2 (1')
wherein V1 is a potential of the power supply terminal 1, and Vtp is a threshold voltage of the P-channel FET T11.
If an ON-resistance of the N-channel FET T12 is small enough with respect to the resistor R3, the current IR3 can be expressed by the following equation (2). EQU IR3.apprxeq.V1/r3 (2)
wherein r3 is a resistance of the resistor R3.
The dissipation current IA of the power-on signal generating circuit shown in FIG. 1 can be expressed by the equation (3). EQU IA=IR2+IR3={(V1-.vertline.Vtp.vertline.)/r2}+(V1/r3) (3)
Accordingly, as is apparent from the above equation (3), the dissipation current increases in proportion with the increase of the power supply voltage V1. Therefore, the resistance value must be increased in order to decrease the dissipation current. However, if the resistance value is increased, there is a drawback that the area is increased when the power-on signal generating circuit is implemented with an integrated circuit.